Greetings from the Contingent, The journey to gold continues. As we progress in our preparation for Inter IIT Tech Meet 14.0, we now take on the first Low-Prep challenge, this time in the Cybersecurity domain presented by QTrino Labs. The Low-Prep Problem Statement titled: PQC-DTLS for Bare-Metal RISC-V IoT Devices, has been released. This challenge focuses on designing and implementing a quantum-safe secure communication protocol for highly constrained embedded systems using post-quantum cryptography. Short Summary of the Problem Statement: The task is to design and demonstrate a post-quantum secure DTLS 1.3 communication channel with full mutual authentication between a server and a RISC-V based IoT device running in a bare-metal environment without an operating system. Participants must integrate PQC algorithms into DTLS 1.3, optimize cryptographic operations for lightweight RISC-V hardware, and establish a functional secure session with efficiency in latency, memory and compute usage. The implementation must demonstrate successful PQC-DTLS handshake and secure communication on the LiteX + Verilator RISC-V platform. (Reference: uploaded document PQTrinoLabs_L1_TechMeet14.pdf) Key Functional Goals: • Perform PQC-DTLS 1.3 handshake between client and server • Integrate a PQC KEM such as Kyber and optionally a PQC signature scheme such as Dilithium • Demonstrate successful secure session establishment with packet traces (Wireshark) • Optimize for latency, RAM/ROM, and CPU cycles on bare-metal RISC-V • Provide clear build and run instructions and a short technical report Skills Required: • Cryptography and secure protocol implementation • Embedded systems and bare-metal firmware • RISC-V architecture and LiteX + Verilator simulation • wolfSSL / wolfCrypt library usage • Networking and DTLS 1.3 fundamentals Problem Statement- https://drive.google.com/file/d/1S9U4LZnUW44EJVycu9_XNWnCth0sRWKd/view?usp=sharing Deliverables: • Working RISC-V bare-metal firmware initiating PQC-DTLS client handshake • Client-server communication demo running in LiteX + Verilator • Packet capture screenshots showing DTLS 1.3 handshake • README with build and run instructions • Configuration and supporting files • Technical report (2-3 pages) describing design, PQC choices, challenges, performance results and optimizations Evaluation Criteria includes latency, throughput, memory usage, CPU efficiency, correctness, optimization quality, reliability under constraints, and clarity of the report and demonstration. Deadline: 11:59 PM, 28th November (strict and non-extendable) Form Link (fill with LDAP): https://forms.gle/GJ7WDYXAo1WV8fdx6 Let us push forward with engineering excellence in secure systems, embedded hardware, and post-quantum cryptography, and continue leading IIT Bombay toward gold. Anirudh Garg | Ayush Prasad Contingent Leaders – B76 Inter IIT Tech Meet 14.0 99151 59599 | 63535 03341 Regards, Shahu Patil General Secretary Technical Affairs 25-26, IIT Bombay Contact: +91 91460 50850 https://tech-iitb.org https://insti.app/org/techiitb