Greetings from the Contingent! The journey to gold continues. As we move forward in our preparation for Inter IIT Tech Meet 14.0, it’s time to take on our next challenge — this time, from ISRO. The Mid-Prep Problem Statement by ISRO – “Delta-Sigma ADC ASIC Design” – has just been released. This challenge calls on electronics enthusiasts and digital design innovators to design and simulate a high-performance Delta-Sigma Analog-to-Digital Converter (ADC) that pushes the limits of resolution and sampling speed. Short Summary of the Problem Statement: Your mission is to study, simulate, and implement an HDL-based design of a Delta-Sigma ADC. The goal is to achieve higher Effective Number of Bits (ENOB) at higher sampling rates through optimized Delta-Sigma modulator and digital decimation filter architectures. You’ll explore different modulator and filter orders/taps to improve resolution, noise shaping, and overall converter performance — bridging the gap between analog signal theory and digital implementation in modern communication, control, and instrumentation systems. Skills Required: • Digital Signal Processing (DSP) and Filter Design • Analog–Digital Conversion Theory and Modulator Design • HDL Implementation and Simulation Problem Statement Link: https://drive.google.com/file/d/1DNV0Be6Lv23gyxcAWs-imLDRjq_-OkcE/view?usp=sharing Form Link (fill with LDAP): https://docs.google.com/forms/d/e/1FAIpQLScIDVix47xQ4zr4QOA8AnSwAcpiEsWR7Djd7WIPDopuddOCXQ/viewform Deadline: 11:59 PM, 9th November 2025 (strict, non-extendable) Join us as we combine signal processing, digital hardware design, and innovation at the silicon level — paving IIT Bombay’s path to gold through precision and engineering excellence. Anirudh Garg | Ayush Prasad Contingent Leaders – B76 Inter IIT Tech Meet 14.0 99151 59599 | 63535 03341 Regards, Shahu Patil, General Secretary Technical Affairs 25-26, IIT Bombay, contact- +91 91460 50850, https://tech-iitb.org https://insti.app/org/techiitb